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74F433 First-In First-Out (FIFO) Buffer Memory
April 1988 Revised October 2000
74F433 First-In First-Out (FIFO) Buffer Memory
General Description
The 74F433 is an expandable fall-through type high-speed First-In First-Out (FIFO) Buffer Memory that is optimized for high-speed disk or tape controller and communication buffer applications. It is organized as 64-words by 4-bits and may be expanded to any number of words or any number of bits in multiples of four. Data may be entered or extracted asynchronously in serial or parallel, allowing economical implementation of buffer memories. The 74F433 has 3-STATE outputs that provide added versatility, and is fully compatible with all TTL families.
Features
s Serial or parallel input s Serial or parallel output s Expandable without additional logic s 3-STATE outputs s Fully compatible with all TTL families s Slim 24-pin package s 9423 replacement
Ordering Code:
Order Number 74F433SPC Package Number N24C Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
(c) 2000 Fairchild Semiconductor Corporation
DS009544
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74F433
Unit Loading/Fan Out
U.L. Pin Names PL CPSI IES TTS MR OES TOP TOS CPSO OE D0-D3 DS Q0-Q3 QS IRF ORE Description HIGH/LOW Parallel Load Input Serial Input Clock Serial Input Enable Transfer to Stack Input Master Reset Serial Output Enable Transfer Out Parallel Transfer Out Serial Serial Output Clock Output Enable Parallel Data Inputs Serial Data Input Parallel Data Outputs Serial Data Output Input Register Full Output Register Empty 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 285/10 285/10 20/5 20/5 Input IIH/IIL Output IOH/IOL 20 A/400 A 20 A/400 A 20 A/400 A 20 A/400 A 20 A/400 A 20 A/400 A 20 A/400 A 20 A/400 A 20 A/400 A 20 A/400 A 20 A/400 A 20 A/400 A 5.7 mA/16 mA 5.7 A/16 mA 400 A/8 mA 400 A/8 mA
Block Diagram
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74F433
Functional Description
As shown in the block diagram, the 74F433 consists of three sections: 1. An Input Register with parallel and serial data inputs, as well as control inputs and outputs for input handshaking and expansion. 2. A 4-bit-wide, 62-word-deep fall-through stack with selfcontained control logic. 3. An Output Register with parallel and serial data outputs, as well as control inputs and outputs for output handshaking and expansion. These three sections operate asynchronously and are virtually independent of one another. Input Register (Data Entry) The Input Register can receive data in either bit-serial or 4bit parallel form. It stores this data until it is sent to the fallthrough stack, and also generates the necessary status and control signals. This 5-bit register (see Figure 1) is initialized by setting flipflop F3 and resetting the other flip-flops. The Q-output of the last flip-flop (FC) is brought out as the Input Register Full (IRF) signal. After initialization, this output is HIGH. Parallel Entry--A HIGH on the Parallel Load (PL) input loads the D0-D3 inputs into the F0-F3 flip-flops and sets the FC flip-flop. This forces the IRF output LOW, indicating that the input register is full. During parallel entry, the Serial Input Clock (CPSI) input must be LOW. Serial Entry--Data on the Serial Data (DS) input is serially entered into the shift register (F3, F2, F1, F0, FC) on each HIGH-to-LOW transition of the CPSI input when the Serial Input Enable (IES) signal is LOW. During serial entry, the PL input should be LOW. After the fourth clock transition, the four data bits are located in flip-flops F0-F3. The FC flip-flop is set, forcing the IRF output LOW and internally inhibiting CPSI pulses from affecting the register. Figure 2 illustrates the final positions in an 74F433 resulting from a 256-bit serial bit train (B0 is the first bit, B255 the last).
FIGURE 1. Conceptual Input Section
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74F433
Functional Description
(Continued) fer, ORE goes HIGH, indicating valid data on the data outputs (provided that the 3-STATE buffer is enabled). The TOP input can then be used to clock out the next word. When TOP goes LOW, ORE also goes LOW, indicating that the output data has been extracted; however, the data itself remains on the output bus until a HIGH level on TOP permits the transfer of the next word (if available) into the output register. During parallel data extraction, the serial output clock (CPSO) line should be LOW. The Transfer Out Serial (TOS) line should be grounded for single-slice operation or connected to the appropriate ORE line for expanded operation (refer to the "Expansion" section). The TOP signal is not edge-triggered. Therefore, if TOP goes HIGH before data is available from the stack but data becomes available before TOP again goes LOW, that data is transferred into the output register. However, internal control circuitry prevents the same data from being transferred twice. If TOP goes HIGH and returns to LOW before data is available from the stack, ORE remains LOW, indicating that there is no valid data at the outputs. Serial Extraction--When the FIFO is empty after a LOW is applied to the MR input, the ORE output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the output register, if the TOS input is LOW and TOP is HIGH. As a result of the data transfer, ORE goes HIGH, indicating that valid data is in the register. The 3-STATE Serial Data Output (QS) is automatically enabled and puts the first data bit on the output bus. Data is serially shifted out on the HIGH-to-LOW transition of CPSO. To prevent false shifting, CPSO should be LOW when the new word is being loaded into the output register. The fourth transition empties the shift register, forces ORE LOW, and disables the serial output, QS. For serial operation, the ORE output may be tied to the TOS input, requesting a new word from the stack as soon as the previous one has been shifted out. Expansion Vertical Expansion--The 74F433 may be vertically expanded, without external components, to store more words. The interconnections necessary to form a 190-word by 4-bit FIFO are shown in Figure 4. Using the same technique, any FIFO of (63n+1)-words by 4-bits can be configured, where n is the number of devices. Note that expansion does not sacrifice any of the 74F433 flexibility for serial/parallel input and output.
FIGURE 2. Final Positions in an 74F433 Resulting from a 256-Bit Serial Train Fall-Through Stack--The outputs of flip-flops F0-F3 feed the stack. A LOW level on the Transfer to Stack (TTS) input initiates a fall-through action; if the top location of the stack is empty, data is loaded into the stack and the input register is re-initialized. (Note that this initialization is delayed until PL is LOW). Thus, automatic FIFO action is achieved by connecting the IRF output to the TTS input. An RS-type flip-flop (the initialization flip-flop) in the control section records the fact that data has been transferred to the stack. This prevents multiple entry of the same word into the stack even though IRF and TTS may still be LOW; the initialization flip-flop is not cleared until PL goes LOW. Once in the stack, data falls through automatically, pausing only when it is necessary to wait for an empty next location. In the 74F433, the master reset (MR) input only initializes the stack control section and does not clear the data. Output Register The Output Register (see Figure 3) receives 4-bit data words from the bottom stack location, stores them, and outputs data on a 3-STATE, 4-bit parallel data bus or on a 3-STATE serial data bus. The output section generates and receives the necessary status and control signals. Parallel Extraction--When the FIFO is empty after a LOW pulse is applied to the MR input, the Output Register Empty (ORE) output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the output register, if the Transfer Out Parallel (TOP) input is HIGH. As a result of the data trans-
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74F433
Functional Description
(Continued)
FIGURE 3. Conceptual Output Section
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74F433
Functional Description
(Continued)
FIGURE 4. A Vertical Expansion Scheme Horizontal Expansion--The 74F433 can be horizontally expanded, without external logic, to store long words (in multiples of 4-bits). The interconnections necessary to form a 64-word by 12-bit FIFO are shown in Figure 5. Using the same technique, any FIFO of 64-words by 4n-bits can be constructed, where n is the number of devices. The right-most (most significant) device is connected to the TTS inputs of all devices. Similarly, the ORE output of the most significant device is connected to the TOS inputs of all devices. As in the vertical expansion scheme, horizontal expansion does not sacrifice any of the 74F433 flexibility for serial/parallel input and output. www.fairchildsemi.com 6 It should be noted that the horizontal expansion scheme shown in Figure 5 exacts a penalty in speed. Horizontal and Vertical Expansion--The 74F433 can be expanded in both the horizontal and vertical directions without any external components and without sacrificing any of its FIFO flexibility for serial/parallel input and output. The interconnections necessary to form a 127-word by 16bit FIFO are shown in Figure 6. Using the same technique, any FIFO of (63m+1)-words by 4n-bits can be configured, where m is the number of devices in a column and n is the number of devices in a row. Figure 7 and Figure 8 illustrate the timing diagrams for serial data entry and extraction for
74F433
Functional Description
(Continued) the FIFO shown in Figure 6. Figure 9 illustrates the final positions of bits in an expanded 74F433 FIFO resulting from a 2032-bit serial bit train.
Interlocking Circuitry--Most conventional FIFO designs provide status signal analogous to IRF and ORE. However, when these devices are operated in arrays, variations in unit-to-unit operating speed require external gating to ensure that all devices have completed an operation. The 74F433 incorporates simple but effective 'master/slave' interlocking circuitry to eliminate the need for external gating. In the 74F433 array of Figure 6, devices 1 and 5 are the row masters; the other devices are slaves to the master in their rows. No slave in a given row initializes its input register until it has received a LOW on its IES input from a row master or a slave of higher priority. Similarly, the ORE outputs of slaves do not go HIGH until their inputs have gone HIGH. This interlocking scheme ensures that new input data may be accepted by the array when the IRF output of the final slave in that row goes HIGH and that output data for the array may be extracted when the ORE output of the final slave in the output row goes HIGH.
The row master is established by connecting its IES input to ground, while a slave receives its IES input from the IRF output of the next-higher priority device. When an array of 74F433 FIFOs is initialized with a HIGH on the MR inputs of all devices, the IRF outputs of all devices are HIGH. Thus, only the row master receives a LOW on the IES input during initialization. Figure 10 is a conceptual logic diagram of the internal circuitry that determines master/slave operation. When MR and IES are LOW, the master latch is set. When TTS goes LOW, the initialization flip-flop is set. If the master latch is HIGH, the input register is immediately initialized and the initialization flip-flop reset. If the master latch is reset, the input register is not initialized until IES goes LOW. In array operation, activating TTS initiates a ripple input register initialization from the row master to the last slave. A similar operation takes place for the output register. Either a TOS or TOP input initiates a load-from-stack operation and sets the ORE request flip-flop. If the master latch is set, the last output register flip-flop is set and the ORE line goes HIGH. If the master latch is reset, the ORE output is LOW until a Serial Output Enable (OES) input is received.
FIGURE 5. A Horizontal Expansion Scheme
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74F433
Functional Description
(Continued)
FIGURE 6. A 127 x 16 FIFO Array
FIGURE 7. Serial Data Entry for Array of Figure
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74F433
Functional Description
(Continued)
FIGURE 8. Serial Data Extraction for Array of Figure
FIGURE 9. Final Position of a 2032-Bit Serial Input
FIGURE 10. Conceptual Diagram, Interlocking Circuitry 9 www.fairchildsemi.com
74F433
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA)
-65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C
+4.5V to +5.5V
-0.5V to VCC -0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS ICC Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Power Supply Current -20 150 4.75 3.75 -0.4 50 -50 -130 215 10% VCC 2.4 2.4 2.7 2.7 0.50 5.0 7.0 50 V A A A V A mA A A mA mA Min Max Max Max 0.0 0.0 Max Max Max Max Max V Min Min 2.0 0.8 -1.5 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = 400 A (ORE, IRF) IOH = 5.7 mA (Qn, Qs) IOH = 400 A (ORE, IRF) IOH = 5.7 mA (Qn, Qs) IOL = 16 mA (Qn, Qs) VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 2.7V (Qn, Qs) VOUT = 0.5V (Qn, Qs) VOUT = 0V
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74F433
AC Electrical Characteristics
TA = +25C Symbol Parameter VCC = +5.0V CL = 50 pF Min tPHL tPLH tPLH tPHL tPLH tPHL tPHL tPHL tPLH tPLH tPHL tPLH tPLH Propagation Delay, Negative-Going CPSI to IRF Output Propagation Delay, Negative-Going TTS to IRF Propagation Delay, Negative-Going CPSO to QS Output Propagation Delay, Positive-Going TOP to Q0-Q3 Outputs Propagation Delay, Negative-Going CPSO to ORE Propagation Delay, Negative-Going TOP to ORE Propagation Delay, Positive-Going TOP to ORE Propagation Delay, Negative-Going TOS to Positive-Going ORE Propagation Delay, PositiveGoing PL to Negative-Going IRF Propagation Delay, NegativeGoing PL to Positive-Going IRF Propagation Delay, Positive-Going OES to ORE tPLH tPHL tPLH tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tPZH tPZL tDFT tAP tAS Propagation Delay Positive-IRF Going IES to Positive-Going Propagation Delay MR to ORE Propagation Delay MR to IRF Enable Time OE to Q0-Q3 Disable Time OE to Q0-Q3 Enable Time Negative-Going OES to QS Disable Time Negative-Going OES to QS Enable Time TOS to QS Fall-Through Time Parallel Appearance Time ORE to Q0-Q3 Serial Appearance Time ORE to QS 2.0 9.0 4.0 5.0 8.0 7.0 7.0 6.0 13.0 13.0 4.0 7.0 9.0 Max 17.0 34.0 25.0 20.0 35.0 30.0 25.0 26.0 48.0 45.0 22.0 31.0 38.0 TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 2.0 8.0 3.0 5.0 7.0 7.0 6.0 6.0 12.0 12.0 4.0 6.0 8.0 Max 18.0 ns 38.0 27.0 21.0 38.0 32.0 28.0 28.0 ns 51.0 50.0 23.0 ns 35.0 44.0 ns Figures 17, 18 ns Figures 13, 14 Figure 15 ns ns ns Figures 13, 14 Figure 15 Figures 13, 14 Figures 11, 12 Units Figure Number
5.0 7.0 5.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 0.2 -20.0 -20.0
25.0 28.0 27.0 16.0 14.0 10.0 23.0 10.0 14.0 10.0 14.0 35.0 35.0 0.9 -2.0 5.0
5.0 7.0 5.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 0.2 -20.0 -20.0
27.0 31.0 30.0 18.0 16.0 12.0 30.0 12.0 15.0 12.0 16.0 42.0 39.0 1.0 -2.0
ns ns ns
Figure 18
ns
ns
ns ns Figure 16
ns 5.0
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74F433
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(L) Setup Time, HIGH or LOW DS to Negative CPSI Hold Time, HIGH or LOW DS to CPSI Setup Time, LOW TTS to IRF, Serial or Parallel Mode tS(L) tS(L) tS(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(H) tW(L) Setup Time, LOW Negative-Going ORE to Negative-Going TOS Setup Time, LOW Negative-Going IES to CPSI Setup Time, LOW Negative-Going TTS to CPSI Setup Time, HIGH or LOW Parallel Inputs to PL Hold Time, HIGH or LOW Parallel Inputs to PL CPSI Pulse Width HIGH or LOW PL Pulse Width, HIGH TTS Pulse Width, LOW Serial or Parallel Mode tW(L) tW(H) tW(L) tW(H) tW(L) tREC MR Pulse Width, LOW TOP Pulse Width HIGH or LOW CPSO Pulse Width HIGH or LOW Recovery Time MR to Any Input 7.0 7.0 14.0 7.0 14.0 7.0 8.0 9.0 9.0 16.0 7.0 16.0 7.0 15.0 ns ns ns 0.0 0.0 ns 7.0 7.0 2.0 2.0 Max TA = 0C to +70C VCC = +5.0V Min 7.0 7.0 2.0 2.0 Figures 11, 12, 17, 18 Figures 13, 14 ns Figures 11, 12 Max Units Figure Number
0.0 8.0 30.0 0.0 0.0 4.0 4.0 10.0 5.0 7.0
0.0 9.0
ns
ns 33.0 0.0 0.0 4.0 4.0 11.0 6.0 9.0 ns ns ns
Figure 12
Figures 11, 12 Figures 17, 18 Figures 11, 12, 13, 14 Figure 16 Figure 15 Figures 13, 14 Figure 16
ns ns
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74F433
Timing Waveforms
Conditions: Stack not full, IES, PL LOW
FIGURE 11. Serial Input, Unexpanded or Master Operation
Conditions: Stack not full, IES HIGH when initiated, PL LOW
FIGURE 12. Serial Input, Expanded Slave Operation
Conditions: Data in stack, TOP HIGH, IES LOW when initiated, OES LOW
FIGURE 13. Serial Output, Unexpanded or Master Operation
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74F433
Timing Waveforms
(Continued)
Conditions: Data in stack, TOP HIGH, IES HIGH when initiated
FIGURE 14. Serial Output, Slave Operation
Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack
FIGURE 15. Parallel Output, 4-Bit Word or Master in Parallel Expansion
Conditions: TTS connected to IRF, TOS connected to ORE, IES, OES, OE, CPSO LOW, TOP HIGH
FIGURE 16. Fall Through Time
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74F433
Timing Waveforms
(Continued)
Conditions: Stack not full, IES LOW when initialized
NOTE A: TTS normally connected to IRF. NOTE B: If stack is full, IRF will stay LOW. FIGURE 17. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion
Conditions: Stack not full, device initialized (Note 3) with IES HIGH Note 3: Initialization requires a master reset to occur after power has been applied.
FIGURE 18. Parallel Load, Slave Mode
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74F433 First-In First-Out (FIFO) Buffer Memory
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 16 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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